NeuReality’s First AI Inference Server-on-a-Chip Validated, Moved to Production
moves to TSMC manufacturing facility, hoping for higher performance, more affordable, and easier-to-use data center infrastructure that unlocks the full potential of AI inference
Cybertech
| 18/09/2023
NeuReality leading team. Photo by Yossi Zeliger
Israeli AI technology innovation startup NeuReality, which creates AI platforms for ultra-scalability of real-life AI applications, announced that its 7nm AI-centric NR1 chip moved its final, validated design to TSMC manufacturing, creating the world’s first AI-centric server-on-a-chip (SOC).
NeuReality hopes to transform AI inference solutions used in a wide range of applications – from natural language processing and computer vision to speech recognition and recommendation systems.
With the mass deployment of AI as a service (AIaaS) and infrastructure-hungry applications such as ChatGPT, NeuReality’s solution is crucial for an industry urgently in need of affordable access to modernized, AI inference infrastructure.
In trials with AI-centric server systems, NeuReality’s NR1 chip demonstrated 10 times the performance at the same cost when compared to conventional CPU-centric systems, according to the company.
The NR1 chip represents the world’s first NAPU (or Network Addressable Processing Unit) and will be seen as an antidote to an outdated CPU-centric approach for inference AI, according to Moshe Tanach, Co-Founder and CEO of NeuReality.
“In order for Inference-specific deep learning accelerators (DLA) to perform at full capacity, free of existing system bottlenecks and high overheads, our solution stack, coupled with any DLA technology out there, enables AI service requests to be processed faster and more efficiently," Tanach said.
Each NR1 chip is a network-attached heterogeneous compute device with multiple tiers of programmable compute engines including a PCIe interface to host any DLA; an embedded Network Interface controller (NIC) and an embedded AI-hypervisor, a hardware-based sequencer that controls the compute engines and shifts data structures between them.
“We are excited about our first generation NAPU product, proven, tested, and ready to move to manufacture. It’s full steam ahead as we reach this highly anticipated manufacturing stage with our TSMC partners. Our plan remains to start shipping products directly to customers by the end of the year,” says Tanach.
moves to TSMC manufacturing facility, hoping for higher performance, more affordable, and easier-to-use data center infrastructure that unlocks the full potential of AI inference
NeuReality leading team. Photo by Yossi Zeliger
Israeli AI technology innovation startup NeuReality, which creates AI platforms for ultra-scalability of real-life AI applications, announced that its 7nm AI-centric NR1 chip moved its final, validated design to TSMC manufacturing, creating the world’s first AI-centric server-on-a-chip (SOC).
NeuReality hopes to transform AI inference solutions used in a wide range of applications – from natural language processing and computer vision to speech recognition and recommendation systems.
With the mass deployment of AI as a service (AIaaS) and infrastructure-hungry applications such as ChatGPT, NeuReality’s solution is crucial for an industry urgently in need of affordable access to modernized, AI inference infrastructure.
In trials with AI-centric server systems, NeuReality’s NR1 chip demonstrated 10 times the performance at the same cost when compared to conventional CPU-centric systems, according to the company.
The NR1 chip represents the world’s first NAPU (or Network Addressable Processing Unit) and will be seen as an antidote to an outdated CPU-centric approach for inference AI, according to Moshe Tanach, Co-Founder and CEO of NeuReality.
“In order for Inference-specific deep learning accelerators (DLA) to perform at full capacity, free of existing system bottlenecks and high overheads, our solution stack, coupled with any DLA technology out there, enables AI service requests to be processed faster and more efficiently," Tanach said.
Each NR1 chip is a network-attached heterogeneous compute device with multiple tiers of programmable compute engines including a PCIe interface to host any DLA; an embedded Network Interface controller (NIC) and an embedded AI-hypervisor, a hardware-based sequencer that controls the compute engines and shifts data structures between them.
“We are excited about our first generation NAPU product, proven, tested, and ready to move to manufacture. It’s full steam ahead as we reach this highly anticipated manufacturing stage with our TSMC partners. Our plan remains to start shipping products directly to customers by the end of the year,” says Tanach.
